Computer Method for Short Circuit Calculations | Electrical Engineering

Digital computer may be defined as a device that can compute by arithmetic processes. The basic processes used are addition and subtraction. These processes are also used in successive approximation or interaction to obtain function values, integration, solution of algebraic equations and linear and nonlinear differential equations. The input data describing the system is specified using the names of power stations, names of sub-stations, data of system components, voltage levels, reactances etc.

Since the short circuit level is normally required at all busbars it is imperative to use the system neutral as reference. Source in-feeds are represented with their equivalent impedances connected between the source busbar and the system neutral.

An admittance matrix, extended to include the source admittances, is formed, and the computation process reduces the extended network to a single impedance connected between the neutral (zero node) and the point of fault.

During this phase sequential bus numbers are assigned, network data is rearranged to facilitate formation of admittance matrices and excessive data checks are performed. Flow chart diagram for digital computer short circuits calculations is shown in Fig. 5.32.

If the faulty busbar voltage is assumed to be 1 pu, then as previously discussed the pu short circuit MVA is given by 1/z_f where z_f has been appropriately extracted from the inverse of |Z| of the extended admittance matrix |Y|. The actual MVA is given by –

 

Example:

Single line diagram of a simple 3-phase 13.8 kV power system is shown in Fig. 5.33:

The details are given below:

Generators G₁ and G₂, both 40 MVA, 0.2 pu

Synchronous motors M₁ and M₂ both 25 MVA, 0.125 pu

Transmission lines AB, CD, AC, BD, 1.9 Ω each.

Determine symmetrical short circuit level at each of the busbars.

Neglect losses and assume that the excitation of each machine is such as to generate normal voltage on no load, and that each machine is running at synchronous speed during the short circuit period.

Solution:

Let the base MVA be 100 MVA, base kV be 13. 8 kV (line-to-line)

Reactances of generators (G₁ and G₂) = [(100/40) x 0.2] = j 0.5 pu each

Reactance of motor (M₁ and M₂) = [(100/25) x 0.125] = j 0.5 pu each

Impendence of transmission lines AB, CD, and BD

= [(j 1.9 x 100)/13.8²] = j 1.0 pu each

Admittances of generators (G₁ and G₂) = 1/j 0.5 = – j 2.0 pu each

Admittances of motors (M₁ and M₂) = 1/j 0.5 = – j 2.0 pu each

Admittances of transmission lines AB, CD and BD

1/j 1.0 = – j 1.0 pu each

Single line diagram showing relevant impedances is shown in Fig. 5.34:

Consider a short circuit on busbar A. A resulting network to be solved for nodal analysis is shown in Fig. 5.35 from which the extended admittance matrix is formed.

The standard matrix representation for nodal analysis becomes of the form –

When applying such analysis to a particular network, unconnected members will be zero inside the admittance matrix:

Now, at all nodes except the faulty node, the injected current is zero.

Inversion of the above admittance matrix provides –

Extracting V_A from above equation, we have –

i.e., the system has effectively been reduced to single impedance between the zero nodes and the point of fault as shown in fig. 5.36:

In this example, the symmetry of the values was intentionally chosen so as to make the short circuit level at each busbar the same.

Short circuit MVA = 1/0.291 = 3.436 pu or 3.436 x 100 = 343.6 MVA Ans.

Provision of Data:

It will be appreciated from Fig. 5.32 that data must be compiled in tabular form in the order in which the information is needed. Busbars should be numbered as 1, 2, 3 etc. with a zero designation for the neutral. Lines may be referred to in terms of the connecting busbars A-B where A-B may be read as 1 -2, 2-3, 4-5 etc.

Data information may be drawn up typically as follows:

Number of busbars (except neutral), N = …….

Total number of connecting line admittances and generator infeeds, M = …..

Based MVA, S = ………….

A programme may be written which reads in the data provided and makes use of a standard sub-routine for matrix inversion. Print instructions may be given to print out the short circuit level at all the busbars. If, for any reason, a short circuit level were required part way along a line this could be arranged by introducing a fictitious node at that point.